Voltage referenced single-ended input/output (SE I/O) standards used in double data rate (DDR) memory interfaces requires the use of a reference voltage at a receiver circuit. The level of the reference voltage determines the switching point of the buffer circuit of the receiver circuit. The value of the switching point of the buffer circuit can in turn affect the duty cycle of the output of the buffer circuit. With the increasing speed of memory devices, distortion of the duty cycle becomes a significant factor for the performance of the receiver circuit as indicated by the horizontal width of the “eye.”
Based on a rule of thumb, the receiver reference voltage level is often set at half of the voltage of the power supply. In practice, the duty cycle of the output of the buffer circuit can be affected by many factors. For example, strength imbalance between the transmitter pull-up transistor and pull-down transistor, the voltage difference between the termination voltage (VTT) and the reference voltage, the offset of the receiver input buffer, etc., can affect the duty cycle of the output of the buffer circuit. Variability in the duty cycle of output of the buffer circuit makes determination of an appropriate value of the reference voltage difficult.